A local analysis of an incremental evolutionary tool for processor diagnosis

This paper details an evolutionary tool targeted at increasing the diagnostic power of a set of assembly programs. The underlying evolutionary scheme is quite peculiar in some aspect and present interesting characteristics The effectiveness of the generated set has recently been demonstrated. Here the use of the tool is further motivated through a deep experimental analysis that provides insight on the obtainable results and better explains the design choices. The use of the tool is validated against a widely used microprocessor core and results are provide

An Evolutionary Methodology for Test Generation for Peripheral Cores Via Dynamic FSM Extraction

Traditional test generation methodologies for peripheral cores are performed by a skilled test engineer, leading to long generation times. In this paper a test generation methodology based on an evolutionary tool which exploits high level metrics is presented. To strengthen the correlation between high-level coverage and the gate-level fault coverage, in the case of peripheral cores, the FSMs embedded in the system are identified and then dynamically extracted via simulation, while transition coverage is used as a measure of how much the system is exercised. The results obtained by the evolutionary tool outperform those obtained by a skilled engineer on the same benchmar

Test Program Generation for Communication Peripherals in Processor-Based Systems-on-Chip

Testing communication peripherals in an environment of systems on a chip is particularly challenging. The authors explore two test program generation approaches-one fully automated and one deterministically guided-and propose a novel combination of the two schemes that can be applied in a generic manner on a wide set of communication core

On the Generation of Functional Test Programs for the Cache Replacement Logic

Caches are crucial components in modern processors (both stand-alone or integrated into SoCs) and their test is a challenging task, especially when addressing complex and high-frequency devices. While the test of the memory array within the cache is usually accomplished resorting to BIST circuitry implementing March test inspired solutions, testing the cache controller logic poses some specific issues, mainly stemming from its limited accessibility. One possible solution consists in letting the processor execute suitable test programs, allowing the detection of possible faults by looking at the results they produce. In this paper we face the issue of generating suitable programs for testing the replacement logic in set-associative caches that implement a deterministic replacement policy. A test program generation approach based on modeling the replacement mechanism as a Finite State Machine (FSM) is proposed. Experimental results with a cache implementing a LRU policy are provided to assess the effectiveness of the method